The present invention relates generally to the art of semiconductor devices and more particularly to methods for determining process related charging during semiconductor processing operations.
In the course of manufacturing semiconductor devices, certain processing steps involve the use of electrically charged plasma. Ion implantation, plasma etching, plasma enhanced deposition processes and other charged processing operations may damage semiconductor wafers, and the devices and circuits formed therein. The plasma in such processes includes charged particles, some of which may accumulate on the wafer surface through antenna charging. For example, in back-end-of-line (BEOL) interconnect processing, inter layer dielectric (ILD) material is often deposited using plasma enhanced chemical vapor deposition (PECVD) and etched using plasma based reactive ion etching (RIE).
During interconnect processing, moreover, one or more patterned metal layers are formed over and between ILD layers to electrically connect electrical devices formed on or in the substrate, such as transistors, memory cells, and the like. The electrical terminals of these devices, such as gates, and source/drain regions, are thus often electrically connected to conductive features directly exposed to these back end processes, which operate as charge gathering antennas. As a result, charge accumulating on exposed conductive features may be discharged through the electrical devices to the substrate, sometimes causing damage and/or performance degradation in the electrical devices. Of particular interest is damage or degradation of the gate oxide layer in MOS type transistors fabricated in a wafer.
Various devices have thusfar been developed to measure the resulting voltage potential (or a current flow) between a charge collection area on the surface of the semiconductor device wafer and the substrate during processing operations or steps. Such devices include monitors or sensors located proximate the wafer workpieces during process steps of interest, which provide sensor signals to control systems or user interface devices. The actual charging of the semiconductor wafer is then inferred from the sensor signal. Charge monitoring (CHARM) wafers have been extensively employed in characterizing process related charging levels, which can be inserted into a process chamber to record the charging levels encountered therein. The CHARM test wafers include a series of electrically erasable programmable read only memory (EEPROM) cell charge sensors or detectors connected between the substrate and conductive antenna pads on the CHARM wafer surface. After the process, the status or data of the various EEPROM sensors is measured, and the results are evaluated using commercially available software tools.
Other process charging measurement devices have been developed, which are formed directly in the wafer workpieces or in dedicated test wafers. These in-situ process charging sensors typically consist of dedicated memory cells, such as one or more EEPROM cells formed in the production wafer. For example, one or more such EEPROM memory cells having a stacked gate MOS type transistor operating as voltage or current sensor may be formed in the production wafers, typically during back end interconnect processing. The memory cell type sensor devices are typically fabricated in peripheral areas of the wafer, such as in scribe regions between device dies on a wafer. The status of these in-situ memory cell sensors can then be interrogated before and after a process of interest to ascertain whether process related charging exceeded a threshold value associated with the cell. In this approach, a charge collection electrode is formed on the top of the wafer, and is connected to the control gate of a stacked gate MOS type transistor (EEPROM cell) to collect process related charge during processing, which in turn affects the transistor gate.
As process charge is collected at the wafer surface, the transistor based memory cell measures the resulting voltage potential between the charge collection electrode and the wafer substrate. The voltage potential in the wafer, in turn changes the threshold voltage Vt of the memory cell, and hence the threshold voltage Vt thereof can be measured before and after a plasma related processing step. A comparison of the threshold voltage measurements is then used to estimate the process charging associated with the processing step. A first or initial threshold voltage is programmed prior to exposing the wafer to a plasma related process, typically by probing the wafer and providing a known programming signal to the transistor via the charge collection electrode. At this point, the actual initial threshold voltage is sometimes measured or verified, prior to performing wafer processing steps involving potential wafer charging.
After the processing step or steps of interest, the EEPROM transistor is probed and a second or final threshold voltage is measured. Once the initial and final threshold voltages are determined, the surface potential related to the process can be estimated using a calibration curve or plot of threshold voltage shift versus gate voltage for the EEPROM transistor. In this regard, the estimated gate voltage represents the voltage potential between the charge collection electrode at the wafer surface and the wafer substrate. Where a resistance of known value is provided between the charge collection electrode and the substrate, then the process related current can be determined according to the gate voltage and the known resistance value. In this fashion, EEPROM transistor-based charge detection devices can be used to estimate the charging associated with a particular processing step.
However, EEPROM memory cell type charging sensors, including CHARM test wafers and in-situ EEPROM memory cell sensors suffer from limits in the range of detectable voltages. Such devices, for example, are generally limited to detection of process charging voltages between about xe2x88x9225 and +30 volts. Consequently, these EEPROM type monitor devices are unable to quantify or measure process related potentials above this range. Furthermore, the estimation of charging voltage values typically does not correlate to potential gate oxide damage or degradation in production wafers. In this regard, CHARM wafers in particular, are typically not manufactured according to a particular process flow of interest to a semiconductor manufacturer. Thus, the results obtained therefrom may not indicate potential problems in actual production wafers, or may provide false indications where gate oxide layers and other features of production devices may be unharmed by a process step or steps. Moreover, CHARM type test wafers are not suitable for all process operations. For example, these cannot be used to ascertain charging in deposition processes.
In addition, the threshold voltage of the EEPROM cell type detectors is sensitive to ultra-violet (UV) radiation. As a result, the threshold voltage shift represents both process related charging and exposure of the wafer to UV sources during processing. Thus, it may be difficult or impossible to differentiate between the two in order to accurately quantify the charging in the manufacturing process. The fabrication of in-situ EEPROM memory cell sensors, moreover, is relatively complex, requiring the formation in the wafer of the source, drain, and gate structures of the MOS type transistor, thereby making the manufacturing process more difficult. Furthermore, the above conventional test devices and techniques require multiple steps to pre-program and verify the EEPROM based test devices to a known initial threshold voltage before processing, and to measure the resulting threshold voltage after processing. Thus, there is a need for improved techniques by which the adverse effects of process related charging can be determined or monitored, without the UV sensitivity and voltage range limitations associated with prior in-situ and other charging sensors, and without unduly adding extra production steps to the manufacturing process flow.
The following presents a simplified summary in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention, and is intended neither to identify key or critical elements of the invention, nor to delineate the scope of the invention. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
One aspect of the invention relates to methods for monitoring or determining process related charging in a semiconductor wafer, by which the above mentioned and other shortcomings associated with the prior art may be mitigated or avoided. Ferroelectric (FE) capacitor process charging monitor devices are employed either in-situ in a production wafer or in a dedicated test wafer, which are connected between the wafer substrate and an antenna or other conductive structure exposed to a wafer processing operation of interest. These devices are relatively simple to design and fabricate in production and/or test wafers, and do not suffer from the UV sensitivity problems associated with EEPROM type in-situ or dedicated process monitors. In addition, the FE sensor devices are not limited by the voltage detection ranges achievable in prior transistor-based memory cell charging sensors.
The FE capacitor may be formed, for example, through metal organic chemical vapor deposition (MOCVD) using ferroelectric thin films such as Pb(Zr,Ti)O3 (PZT), (Ba,Sr)TiO3 (BST), SrTiO3 (STO) and SrBi2Ta2O9 (SBT), BaTiO3 (BTO), (Bil-xLax) 4Ti3O12 (BLT), or other ferroelectric material formed between two conductive electrodes in the semiconductor wafer. Ferroelectric materials exhibit electric polarization behavior, wherein an initial polarization can be established or switched (e.g., reversed) by application of a suitable electric field, such as by applying a voltage potential between the antenna and the wafer substrate material. Once a ferroelectric capacitor device is initially polarized, the polarization typically remains until a subsequent switching voltage value of opposite polarity will cause the capacitor polarity to change. Otherwise, once the external voltage is removed, the capacitor generally retains its polarization, at least for a time.
The ferroelectric capacitor is formed in the wafer having substantially no net polarization, and is not prepolarized prior to the process of interest. Thus, the invention may be advantageously employed without significantly increasing the processing time for production wafers. One or more process operations or steps of interest are then performed on the wafer, wherein the ferroelectric device may be fully or partially polarized depending upon the charging levels experienced in the processing. The invention can be employed to quantify process related charging effects associated with any process steps or operations of interest, including deposition processes not previously measurable using conventional CHARM type wafers. For instance, the invention may be employed in determining or monitoring process charging in resist ashing operations, dielectric deposition operations, such as using plasma enhanced chemical vapor deposition (PECVD), metal or dielectric etch operations, such as dry plasma etching, implantation operations, and other process steps in which plasma is employed or other potentially damaging process related wafer charging is experienced or suspected. Further, the invention may facilitate quantification of charging levels in one or more process steps, even where the ferroelectric capacitor does not see a full saturation voltage during processing.
When the processing steps of interest are completed, the process related polarization of the ferroelectric capacitor is ascertained. Process related charging may then be determined based the amount of process related ferroelectric capacitor polarization. In one implementation, a test voltage is applied to the ferroelectric capacitor after the processing step or steps of interest, and the resulting current is measured. Based on this, a charge density is determined, such as through integration of a measured current waveform. The switching charge value for a capacitor of known area, thickness, and ferroelectric material can then be determined and correlated to a J-V (e.g., charge density versus voltage) plot for the ferroelectric capacitor. This then is indicative of a process related voltage level experienced by the ferroelectric capacitor during the processing.
In this regard, the ferroelectric capacitor dielectric material, area, and/or thickness may be selected so as to correspond to a particular gate oxide thickness of interest in the device. Thus, the invention allows quantification of charging levels or values correlated to one or more gate oxides used in transistors of the device. More than one test voltage pulse may be applied post-processing, in order to ascertain the process related polarization of the ferroelectric device. In one implementation, two test voltage pulses are applied, and a corresponding pair of current waveforms are measured. The difference between the charge densities associated with the current waveforms is correlated to a process voltage. A process related current density is determined from the process voltage using a J-V plot (e.g., current density vs. voltage) for the ferroelectric capacitor, by which a point on a process J-V curve is ascertained. From this information, a gate oxide voltage can be determined for a given gate oxide thickness in the wafer, to ascertain whether the process step or steps of interest are potentially damaging to the gate oxide of transistors in the wafer.
The invention may further be employed in association with test or production wafers having a plurality of such ferroelectric charging sensor devices, for example, where the devices have different areas or thicknesses, or were fabricated using different ferroelectric materials. In this manner, charging during processing may cause one level of polarization in some FE capacitors, and different levels of polarization in others. Knowing the device sizes and thicknesses, and the materials associated with the devices facilitates determination of the charging voltage and/or current densities during processing, and the effects thereof on different gate oxides in the wafer.
To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed. Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.